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multistage interconnection networks
Multistage interconnection networks (MINs) are a class of high-speed computer networks usually composed of processing elements (PEs) on one end of the network and memory elements (MEs) on the other end, connected by switching elements (SEs). The switching elements themselves are usually connected to each other in stages, hence the name.
Such networks include networks, omega networks, delta networks and many other types. MINs are typically used in high-performance or parallel computing as a low-latency interconnection (as opposed to traditional packet switching networks), though they could be implemented on top of a packet switching network. Though the network is typically used for routing purposes, it could also be used as a co-processor to the actual processors for such uses as sorting; cyclic shifting, as in a perfect shuffle network; and bitonic sorting.
==Sources ==
*Aljundi, Dekeyser, Kechadi, Scherson, ("A study of an evaluation methodology for unbuffered multistage interconnection networks" (2003) ), ''Proceedings of 17th International Parallel and Distributed Processing Symposium''
* Achille Pattavina, ''Switching Theory: Architecture and Performance in Broadband ATM Networks'', John Wiley & Sons Ltd, 1998, ISBNs: 0-471-96338-0 (Hardback); 0-470-84191-5 (Electronic)
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